1. Technical Field
The present disclosure relates to a switching circuit for a transmission channel for ultrasound applications, inserted between a connection terminal and a low voltage output terminal and comprising a receiving switch.
The disclosure also relates to a transmission channel for ultrasound applications of the type comprising at least such a switching circuit and to a process for driving said switching circuit.
The disclosure particularly, but not exclusively, relates to a switching circuit suitable for being used by a transmission channel for ultrasound applications and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, the sonography or ultrasonography is a system of mechanical diagnostic testing that uses ultrasonic waves or ultrasounds and is based on the principle of the transmission of the ultrasounds and of the emission of echo and is widely used in the internal medicine, surgical and radiological fields.
The ultrasounds normally used are comprised between 2 and 20 MHz. The frequency is chosen by taking into consideration that higher frequencies have a greater image resolving power, but penetrate less in depth in the subject under examination.
Substantially, an ultrasonographer, in particular a diagnostic apparatus based on the ultrasound sonography, comprises three parts:                a probe comprising at least an ultrasonic transducer, in particular of the type realized by means of piezoelectric crystal, which is suitably biased for causing its deformation and the generation of an ultrasound signal or pulse;        an electronic system that drives the transducer for the generation of the ultrasound signal or pulse to be transmitted and that receives an echo signal at the probe, processing in consequence the received echo signal; and        a displaying system able to collect the return signal or echo and to generate a corresponding sonographic image starting from the echo signal received at the probe and shown on a monitor.        
The piezoelectric transducer is equivalent to an electric circuit substantially comprising a capacitor, an inductance and a resistance inserted in series to each other.
A typical transmission/receiving channel or channel TX with three voltage levels used in these applications is schematically shown in FIG. 1 and indicated with 1A.
In particular, the transmission/receiving channel 1A comprises a level shifter 2A, of the type comprising a half-bridge 4 inserted between a first terminal HVP, connected to a positive voltage, and a second terminal HVM, connected to a negative voltage. The voltage of the output terminal HVout of the level shifter 2A is brought by a clamp block 5 to a reference voltage, which, in the present example, is the ground voltage GND.
The clamp block 5A is substantially a high voltage switch between said output terminal HVout of the level shifter 2A and said ground voltage GND, controlled by a first driving signal INC.
The output terminal HVout corresponding to a first output terminal of the transmission channel 1A, is connected to a connection terminal Xdcr for the piezoelectric transducer, to be driven through the transmission channel 1A.
Suitably, an anti-noise block 3, comprising two diodes connected in antiparallel, is inserted between the output terminal VHout of the level shifter 2A and the connection terminal Xdcr. The anti-noise block 3, known as anti-noise diodes, allows during the receiving step of the transmission channel 1A to release the parasitic capacitances of the half-bridge of the level shifter 2A from the connection terminal Xdcr, thus avoiding to influence the receiving signal.
A T/R switch 6A or receiving switch is inserted between the connection terminal Xdcr and a low voltage output terminal LVout of the transmission channel 1. During the receiving step of the transmission channel 1, the receiving switch 6A is activated and transmits the receiving signal to the low voltage output terminal LVout.
The low voltage output terminal LVout is connected to an amplifier LNA that allows to amplify the signals or echoes received by the piezoelectric transducer that are following to the pulses sent. The receiving signal, suitably processed, will allow to display an image on a screen, not shown in the figure.
It is to be noted that the receiving switch 6A is of the high voltage type even if the receiving signal is a signal generally with low voltage value, since the piezoelectric transducer connected to the transmission channel 1A detects small return echoes of ultrasound pulse signals.
It is desirable for the receiving switch 6A to meet two needs that are apparently in contrast with each other: it should be of the high voltage type during the transmission step of the transmission channel 1A, in which the level shifter 2A has a step of variable duration between tens and hundreds of nanoseconds, while during the receiving step it should be on always with low voltages, the receiving step can have a duration of some hundreds of microseconds.
Moreover, the receiving switch 6A and the clamp block 5A are generally realized in two separated chips, and in particular connected respectively in a receiving chip and in a transmission chip, or, if present in the same chip they are realized separately so as to correctly respond to the single specifications.
More in detail, according to an embodiment shown in FIG. 2, a clamp block 5B comprises two circuit branches in parallel to each other and inserted between the output terminal HVout and an inner node X1.
The first branch comprising a first buffer diode Db1 and a first clamping transistor Mc1, inserted in series to each other, and the second branch comprises a second clamping transistor Mc2 and a second buffer diode Db2, inserted in series to each other. The inner node X1 is connected to the ground voltage GND.
The first clamping transistor Mc1 is a high voltage transistor MOS and with channel N (HV NMOS) while the second clamping transistor Mc2 is a high voltage MOS transistor with P channel (HV PMOS) and the first and the second buffer diode, Db1 and Db2, are high voltage diodes (HV diode). The first and the second clamping transistors Mc1 and Mc2, have respective control terminals, or gates, connected to a first signal INC1 and to a second signal INC2 respectively through a first and a second input driver, B1 and B2.
This FIG. 2 also shows the drain/source equivalent parasite diodes, Dc1 and Dc2, of the clamping transistors, Mc1 and Mc2.
These two branches allow to clamp the output terminal HVout to the ground voltage GND both for voltage positive values and for voltage negative values. In particular, the first and the second diode, Db1 and Db2, and the parasite diodes, Dc1 and Dc2, allow to support positive and negative voltage values present on the output terminal HVout when the clamp block 5B is off, i.e. with the first and with the second driving signal, INC1 and INC2, deactivated.
The receiving switch 6B comprises a first receiving transistor Mr1, and a second receiving transistor Mr2 in series to each other and respectively connected to the connection terminal Xdcr and to the low voltage output terminal LVout of the transmission channel 1. The first receiving transistor Mr1 is a high voltage MOS transistor with P channel (HV PMOS) and the second receiving transistor Mr2 is a high voltage transistor MOS and with channel N (HV Nmos). The first and the second receiving transistor Mr1 and Mr2 have respective control terminals, or gates, respectively connected to a first signal INSW1 and to a second driving signal INSW2.
This FIG. 2 also shows the drain/source equivalent parasite diodes, Dr1 and Dr2 respectively of the first and of the second receiving transistor, Mr1 and Mr2.
As regards the operation of the receiving switch 6B, during the receiving step of the transmission channel 1 the two receiving transistors Mr1 and Mr2 are on. While, in the transmission step, the two receiving transistors Mr1 and Mr2 will have to be off and thus the respective control voltage, or gate-source voltage |Vgs|, will have to be null. Thus, in this step on the control terminal of the first transistor Mr1 and on the first control terminal, or source terminal (VSP), the positive voltage variations will follow the voltage variations of the connection terminal Xdcr.
The first and the second receiving transistor, Mr1 and Mr2 typically are sized so as to have a respective input resistance Ron compatible with the noise specifications preset.
The value of the input resistance Ron of the receiving switch 6B significantly affects the performances at the receiving.
In fact, the charge stored in the capacitor of the piezoelectric transducer is injected on the connection terminal Xdcr during the turn-on and receiving steps of the transmission channel 1B and this could cause noise and thus potential disturbances that affect the signal transmitted or received by the transmission channel 1 generating a malfunction.
Moreover, it is to be noted that, during the receiving step, the capacitor of the piezoelectric transducer is in parallel to the input resistance Ron of the receiving switch and thus could disturb the receiving signal received by the connection terminal Xdcr of the transmission channel 1B.
A transmission/receiving channel 1C with five voltage levels for ultrasound applications is shown in FIG. 3.
The transmission channel 1C, similarly to what has been previously shown and described, comprises a level shifter 2C connected to the output terminal HVout with a clamp block 5A and connected to a connection terminal Xdcr through an anti-noise block 3. Moreover, the output terminal HVout is connected to a low voltage output terminal LVout of the transmission channel 1C by means of a receiving switch 6A.
The level shifter 2C comprises a half-bridge 4 and a further half-bridge 4′ inserted between two first terminals, HVP0 and HVP1, connected to two positive voltages, independent from each other, and two second terminals, HVM0 and HVM1, connected to two negative voltages, independent from each other.
The voltage present at the output terminal HVout of the level shifter 2C is brought through the clamp block 5A to a ground voltage GND, while the receiving switch 6A transmits the signal received by the connection terminal Xdcr to the low voltage output terminal LVout.